A NAND flash EEPROM (Electrically Erasable and Programmable Read Only Memory) has been known as a nonvolatile semiconductor storage device that is capable of electrical rewriting and high integration. The NAND flash EEPROM includes a memory cell array region having a plurality of memory cells capable of storing data therein and a peripheral circuit region for controlling memory cell array. STI (Shallow Trench Isolation) is provided as an element isolation between memory cells adjacent to each other in a word line direction.
A trench of STI is sometimes formed continuously in the same process as that of processing a floating gate. In this case, after a tunnel dielectric film is formed on a semiconductor substrate, a material for the floating gate is deposited. Thereafter, the trench of STI is also formed simultaneously with the process of the floating gate. By burying an insulating film in the trench, STI is formed.
When the trench of STI is formed simultaneously with the process of the floating gate as explained above, the number of manufacturing processes can be reduced, but the floating gate, the tunnel dielectric film, and the semiconductor substrate (an active area) are tapered forward. In this case, a bottom surface of the floating gate is inevitably narrower than a top surface of the active area.
A flash memory extracts electric charges in the floating gate by applying a large voltage (for example, 20 V) between the control gate and the semiconductor substrate in a data deletion operation. As explained above, when a large voltage is applied between the semiconductor substrate and the floating gate, a large electric field easily concentrates between a bottom end part of the floating gate and the active area. When the bottom surface of the floating gate is narrower than the top surface of the active area and the bottom end part of the floating gate is on the top surface of the active area as explained above, a larger electric field concentrates on the bottom end part of the floating gate. In this case, electric charges are easily trapped by the bottom end part of the floating gate and the tunnel dielectric film is easily broken.